//
// ちょうど 真ん中だね。
//
module TRAGI (
input wire reset, // reset信号
input wire clock, // clock
input wire [7:0] DIP_SW, // ボード上のDIP SW
output reg [7:0] LED // ボード上のLED
);
reg [24:0] count; // counter
reg clock_0.5sec;
always @ ( negedge reset or posedge clock ) begin
if( reset == 1'b0 ) begin
counter <= 0;
clock_0.5sec <= 0;
end else begin
if( counter < 12000000 ) begin
clock_0.5sec <= 1'b1;
end else if( counter < 24000000 ) begin
clock_0.5sec <= 1'b0;
end else begin
counter <= 0;
end
end
end
reg clock_0.5sec_zenkai;
always @ ( negedge reset or posedge clock ) begin
if( reset == 1'b0 ) begin
LED <= 8'b1;
end else begin
if( clock_0.5sec_zenkai==1'b0) && (clock_0.5sec==1'b1) ) begin
// LED <= { LED[6:0], 1'b0 }; //
LED <= { LED[6:0], LED[7] }; // バーレルshifter
end
end
clock_0.5sec_zenkai <= clock_0.5sec;
end
endmodule